1. Technical Field
This disclosure relates generally to processing workpieces, such as high-precision wafers and substrates, and in particular to a method and apparatus of processing workpieces more efficiently and cost-effectively on a single machine.
2. State of the Art
Wafer back grinding, also known as wafer thinning, is a semiconductor device fabrication step during which wafer thickness is reduced to allow for stacking and high density packaging of integrated circuits (IC). These integrated circuits are present in many everyday electrical-based and electronic-enabled devices.
The fabrication of semiconductor devices is typically a multiple-step sequence of photographic and chemical processing stages/phases during which electronic circuits are gradually created on a wafer made of semiconducting material. The semiconductor device fabrication process is continually evolving, in most every phase, in an effort to obtain increased efficiencies, cost savings, and size reductions. For example, as electronics applications shrink in size, integrated circuit (IC) packaged devices must be reduced both in footprint and thickness. The main motivation for the development of smaller packages is the demand for portable communications devices, such as memory cards, smart cards, cellular telephones, portable computing and so forth.
Because of its high thinning rate, mechanical grinding currently is the most common technique for wafer thinning. Surface grinding or polishing operations in semiconductor device fabrication can entail both back grinding and face grinding. Wafer back grinding is a process in semiconductor device fabrication in which the backside of a wafer is ground down to the desired wafer thickness prior to assembly. Wafer back grinding can include both coarse grinding and fine grinding techniques to achieve the optimal wafer thickness and performance for the particular application. On the other hand, wafer face grinding is a process in semiconductor device fabrication in which the front or active surface of the wafer is planarized, or flattened, after each layer is formed on the substrate in order to meet exceedingly stringent flatness requirements necessary for small-dimensioned patterning. Back grinding and face grinding operations, collectively referred to herein as surface grinding, have been implemented in various forms on existing machines.
As processed wafers become thinner, conventional thinning processes put wafer edges at high risk of chipping. In particular, a conventional surface grinding process can produce a wafer in which its edge becomes a protruding and unsupported sharp edge of, for example, silicon, with increased likelihood of chipping. However, such chipping along sharp edges may be reduced by trimming the edge of the wafer prior to surface grinding operations in order to remove rough or damaged surfaces from the edge region of a wafer. The benefits of performing an edge trimming process include a reduction in wafer defects, enable direct wafer bonding, and so forth.
Conventionally, surface grinding and edge trimming processes call for separate machines that each provides a separate and specific function—one machine as a surface grinder and another machine as a wafer edge grinder. But, the need to purchase individual machines to realize these separate processes undesirably increases capital equipment costs, uses excessive space, and increases manufacturing complexity through incorporation of additional process steps.
As a result, there is a need in the wafer fabrication industry and market for an apparatus that addresses these concerns.